PIC12F1822-ISLASHMF datasheet(171/398 Pages) MICROCHIP

171 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 171

PIC12F/LF1822/16F/LF1823

TABLE 19-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

OPTION_REG: OPTION REGISTER

R/W-1/1

WPUEN

INTEDG

TMR0CS

TMR0SE

PSA

PS<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

WPUEN: Weak Pull-up Enable bit

1 = All weak pull-ups are disabled (except MCLR, if it is enabled)

0 = Weak pull-ups are enabled by individual WPUx latch values

bit 6

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RA2/INT pin

0 = Interrupt on falling edge of RA2/INT pin

bit 5

TMR0CS: Timer0 Clock Source Select bit

1 = Transition on RA2/T0CKI pin

0 = Internal instruction cycle clock (FOSC/4)

bit 4

TMR0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on RA2/T0CKI pin

0 = Increment on low-to-high transition on RA2/T0CKI pin

bit 3

PSA: Prescaler Assignment bit

1 = Prescaler is not assigned to the Timer0 module

0 = Prescaler is assigned to the Timer0 module

bit 2-0

PS<2:0>: Prescaler Rate Select bits

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

CPSCON0

CPSON

CPSRM

—

CPSRNG1 CPSRNG0 CPSOUT

T0XCS

313

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE

PSA

PS2

PS1

PS0

171

TMR0

Timer0 Module Register

169*

TRISA

—

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

121

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.

* Page provides register information.

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

Bit Value

Timer0 Rate

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