EM357-RTR datasheet(105/240 Pages) ETC2

105 / 240 page

EM351 / EM357

8-34

120-035X-000D

Preliminary

8.7.1

Registers

SCx_DMACTRL

SC1_DMACTRL

Serial DMA Control Register

Address: 0x4000C830 Reset: 0x0

SC2_DMACTRL

Serial DMA Control Register

Address: 0x4000C030 Reset: 0x0

SC_TXDMARST

SC_RXDMARST

SC_TXLODB

SC_TXLODA

SC_RXLODB

SC_RXLODA

Bitname

Bitfield

Access

Description

SC_TXDMARST

[5]

Setting this bit resets the transmit DMA. The bit clears automatically.

SC_RXDMARST

[4]

Setting this bit resets the receive DMA. The bit clears automatically.

SC_TXLODB

[3]

Setting this bit loads DMA transmit buffer B addresses and allows the DMA controller to

start processing transmit buffer B. If both buffer A and B are loaded simultaneously,

buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this

bit has no effect.

Reading this bit returns DMA buffer status:

0: DMA processing is complete or idle.

1: DMA processing is active or pending.

SC_TXLODA

[2]

Setting this bit loads DMA transmit buffer A addresses and allows the DMA controller to

start processing transmit buffer A. If both buffer A and B are loaded simultaneously,

buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this

bit has no effect.

Reading this bit returns DMA buffer status:

0: DMA processing is complete or idle.

1: DMA processing is active or pending.

SC_RXLODB

[1]

Setting this bit loads DMA receive buffer B addresses and allows the DMA controller to

start processing receive buffer B. If both buffer A and B are loaded simultaneously, buffer

A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has

no effect.

Reading this bit returns DMA buffer status:

0: DMA processing is complete or idle.

1: DMA processing is active or pending.

SC_RXLODA

[0]

Setting this bit loads DMA receive buffer A addresses and allows the DMA controller to

start processing receive buffer A. If both buffer A and B are loaded simultaneously, buffer

A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has

no effect.

Reading this bit returns DMA buffer status:

0: DMA processing is complete or idle.

1: DMA processing is active or pending.

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