EM357-RTR datasheet(155/240 Pages) ETC2

155 / 240 page

EM351 / EM357

9-35

120-035X-000D

Preliminary

Bitname

Bitfield

Access

Description

TIM_ETF

[11:8]

External Trigger Filter.

This defines the frequency used to sample the ETRP signal, Fsampling, and the length of

the digital filter applied to ETRP. The digital filter is made of an event counter in which N

events are needed to validate a transition on the output:

0000: Fsampling=PCLK, no filtering.

0001: Fsampling=PCLK, N=2.

0010: Fsampling=PCLK, N=4.

0011: Fsampling=PCLK, N=8.

0100: Fsampling=PCLK/2, N=6.

0101: Fsampling=PCLK/2, N=8.

0110: Fsampling=PCLK/4, N=6.

0111: Fsampling=PCLK/4, N=8.

1000: Fsampling=PCLK/8, N=6.

1001: Fsampling=PCLK/8, N=8.

1010: Fsampling=PCLK/16, N=5.

1011: Fsampling=PCLK/16, N=6.

1100: Fsampling=PCLK/16, N=8.

1101: Fsampling=PCLK/32, N=5.

1110: Fsampling=PCLK/32, N=6.

1111: Fsampling=PCLK/32, N=8.

Note: PCLK is 12 MHz when the EM35x is using the 24 MHz crystal oscillator, and 6 MHz if

using the 12 MHz RC oscillator.

TIM_MSM

[7]

Master/Slave Mode.

0: No action.

1: The effect of an event on the trigger input (TRGI) is delayed to allow exact

synchronization between the current timer and the slave (through TRGO). It is useful for

synchronizing timers on a single external event.

TIM_TS

[6:4]

Trigger Selection.

This bit field selects the trigger input used to synchronize the counter.

000 : Internal Trigger 0 (ITR0).

100 : TI1 Edge Detector (TI1F_ED).

101 : Filtered Timer Input 1 (TI1FP1).

110 : Filtered Timer Input 2 (TI2FP2).

111 : External Trigger input (ETRF).

Note: These bits must be changed only when they are not used (when TIM_SMS=000) to

avoid detecting spurious edges during the transition.

TIM_SMS

[2:0]

Slave Mode Selection.

When external signals are selected the active edge of the trigger signal (TRGI) is linked to

the polarity selected on the external input.

000: Slave mode disabled.

If TIM_CEN = 1 then the prescaler is clocked directly by the internal clock.

001: Encoder mode 1. Counter counts up/down on TI1FP1 edge depending on TI2FP2

level.

010: Encoder mode 2. Counter counts up/down on TI2FP2 edge depending on TI1FP1

level.

011: Encoder mode 3. Counter counts up/down on both TI1FP1 and TI2FP2 edges

depending on the level of the other input.

100: Reset Mode. Rising edge of the selected trigger signal (TRGI) >reinitializes the

counter and generates an update of the registers.

101: Gated Mode. The counter clock is enabled when the trigger signal (TRGI) is high. The

counter stops (but is not reset) as soon as the trigger becomes low. Both starting and

stopping the counter are controlled.

110: Trigger Mode. The counter starts at a rising edge of the trigger TRGI (but it is not

reset). Only starting the counter is controlled.

111: External Clock Mode 1. Rising edges of the selected trigger (TRGI) clock the counter.

Note: Gated mode must not be used if TI1F_ED is selected as the trigger input

(TIM_TS=100). TI1F_ED outputs 1 pulse for each transition on TI1F, whereas gated mode

checks the level of the trigger signal.

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