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S12OSCV2D Datasheet(PDF) 120 Page - Freescale Semiconductor, Inc |
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S12OSCV2D Datasheet(HTML) 120 Page - Freescale Semiconductor, Inc |
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120 / 126 page ![]() MC9S12DJ64 Device User Guide — V01.17 120 32 D NOACC hold time tNOH 2ns 33 D IPIPO[1:0] delay time tP0D 27 ns 34 D IPIPO[1:0] valid time to E rise (PWEL–tP0D)tP0V 11 ns 35 D IPIPO[1:0] delay time1 (PWEH-tP1V) tP1D 225 ns 36 D IPIPO[1:0] valid time to E fall tP1V 11 ns NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches. Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF Num C Rating Symbol Min Typ Max Unit |
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