AM79C971VCW datasheet(246/265 Pages) AMD

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D-10

Am79C971

Figure D4.

LAPP 3 Buffer Grouping for Two-interrupt Method

Note:

This document demonstrates a 3-buffer per packet implementation of LAPP. For PCnet-FAST application with external SRAMs

enabled, a 2-buffer per packet implementation can be used.

Descriptor

OWN = 1

STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1

STP = 0

SIZE = S1+S2+S3+S4

OWN = 0

STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

OWN = 1

STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1

STP = 0

SIZE = S1+S2+S3+S4

OWN = 0

STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

OWN = 1

STP = 1

SIZE = HEADER_SIZE (minimum 64 bytes)

OWN = 1

STP = 0

SIZE = S1+S2+S3+S4

OWN = 0

STP = 0

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

A = Expected message size in bytes

S1 = Interrupt latency

S2 = Application call latency

S3 = Time needed for driver to write

to third descriptor

S4 = Time needed for driver to copy

data from buffer #1 to

application buffer space

S6 = Time needed for driver to copy

data from buffer #2 to

application buffer space

Note that the times needed for tasks S1,

S2, S3, S4, and S6 should be divided by

0.8 microseconds to yield an equivalent

number of network byte times before

subtracting these quantities from the

expected message size A.

19364D-D4

AM79C971VCW Datasheet(PDF) 246 Page - Advanced Micro Devices

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