RM0319 datasheet(148/368 Pages) STMICROELECTRONICS

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Fast Ethernet port (MII0)

RM0319

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Doc ID 022640 Rev 3

[02]

Excessive Deferral. If set, it indicates that the transmission has ended

because of excessive deferral of over 24288 bit times (155680 bit times in

Jumbo Frame Enabled Mode), if the DC (Deferral Check) bit in the MAC

Configuration register (Register 0) is set.

[01]

Underflow Error. If set, it indicates that the transmission has ended because

data arrived late from the host memory. This means that DMA encountered

an empty Transmit Buffer while transmitting the frame.

[00]

Deferred Bit. If set, it indicates that the MAC defers before transmission

because of the presence of carrier. Valid in half-duplex mode only.

Table 45.

Transmit descriptor 1 (TEDS1)

Bit

Name

Description

[31:29]

Reserved

[28:16]

TBS2

Transmit Buffer 2 Size. These 13 bit field reports the size (in bytes) of the

second data buffer.

Note: This field is not valid if TDES0[20] is set.

[15:13]

Reserved

[12:00]

TBS1

Transmit Buffer 1 Size. These 13 bit field reports the size (in bytes) of the first

data buffer.

Note: If TBS1 value is 13h’0, then the DMA ignores this buffer and uses the

2nd buffer or next descriptor (depending on TCH bit value).

Table 46.

Transmit descriptor 2 (TDES2)

Bit

Name

Description

[31:00]

Buffer 1

Address

Pointer

This field indicates the physical address of the 1st data buffer

pointed to by this descriptor.

Table 47.

Transmit descriptor 3 (TDES3)

Bit

Name

Description

[31:00]

Buffer 2

Address

Pointer

This field indicates the physical address of the 2nd data buffer pointed to

by this descriptor, if descriptor chaining is used.

If TDES1[24] bit is set, then this field contains the pointer to the physical

memory when the next descriptor is present.

Table 44.

Transmit descriptor 0 (TDES0) (continued)

Bit

Name

Description

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