MEC1322 datasheet(146/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 146

 2014 - 2015 Microchip Technology Inc.

11.5

Host Interface

The 8042 interface is accessed by host software via a registered interface, as defined in Section 11.13, "Configuration

Registers" and Section 11.14, "Runtime Registers".

11.6

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

11.6.1

POWER DOMAINS

11.6.2

CLOCK INPUTS

11.6.3

RESETS

11.7

Interrupts

This section defines the Interrupt Sources generated from this block.

11.8

Low Power Modes

The 8042 Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.

TABLE 11-2:

POWER SOURCES

Name

Description

VCC1

This Power Well is used to power the registers and logic in this block.

TABLE 11-3:

CLOCK INPUTS

Name

Description

1MHz

Clock used for the counter in the CPU_RESET circuitry.

TABLE 11-4:

RESET SIGNALS

Name

Description

VCC1_RESET

This reset is asserted when VCC1 is applied.

PWRGD

This signal is asserted when the main power rail is asserted.

PCI RESET#

This signal is asserted when LRESET# is asserted.

nSIO_RESET

This signal is asserted when VCC1 is low, PWRGD is low, or LRESET#

is asserted.

TABLE 11-5:

SYSTEM INTERRUPTS

Source

Description

KIRQ

This interrupt source for the SIRQ logic, representing a Keyboard inter-

rupt, is generated when the PCOBF status bit is ‘1’.

MIRQ

This interrupt source for the SIRQ logic, representing a Mouse interrupt,

is generated when the AUXOBF status bit is ‘1’.

TABLE 11-6:

EC INTERRUPTS

Source

Description

8042EM_IBF

Interrupt generated by the host writing either data or command to the data

8042EM_OBF

Interrupt generated by the host reading either data or aux data from the

data register

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