MEC1322 datasheet(164/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 164

 2014 - 2015 Microchip Technology Inc.

12.10 Description

FIGURE 12-2:

MAILBOX BLOCK DIAGRAM

12.10.1

HOST ACCESS PORT

The Mailbox includes a total of 47 index-addressable 8-bit Mailbox registers and a two byte Mailbox Registers Host

Access Port. Forty-three of the 47 index-addressable 8-bit registers are EC Mailbox registers, which can be read and

written by both the EC and the Host. The remaining four registers are used for signaling between the Host and the EC.

The Host Access Port consists of two 8-bit run-time registers that occupy two addresses in the HOST I/O space, MBX-

_INDEX Register and MBX_DATA Register. The Host Access Port is used by the host to access the 47 index-address-

able 8-bit registers.

To access a Mailbox register once the Mailbox Registers Interface Base Address has been initialized, the Mailbox reg-

ister index address is first written to the MBX Index port. After the Index port has been written, the Mailbox data byte

can be read or written via the MBX data port.

The Host Access Port is intended to be accessed by the Host only, however it may be accessed by the EC at the Offset

shown from its EC base address in Table 12-7, "Runtime Register Base Address Table".

12.10.2

HOST INTERRUPT GENERATION

The Mailbox can generate a SIRQ event for EC-to-HOST EC events, using the EC-to-Host Mailbox Register. This inter-

rupt is routed to the SIRQ block.

The Mailbox can also generate an SMI event, using SMI Interrupt Source Register. The SMI event can be routed to

any frame in the SIRQ stream as well as to the nSMI pin. The SMI event can be routed to nSMI pin by selecting the

nSMI signal function in the associated GPIO Pin Control Register. The SMI event produces a standard active low frame

on the serial IRQ stream and active low level on the open drain nSMI pin.

Routing for both the SIRQ logic and the nSMI pin is shown in Figure 12-3.

HOST-to-EC

EC-to-HOST

Forty-three 8-bit

Mailbox Registers

Host CPU

SMI

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