ADE9078 datasheet(105/108 Pages) AD

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ADE9078

Data Sheet

Rev. 0 | Page 104 of 107

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

[11:9]

HPF_CRN

High-pass filter corner (f3dB) enabled when the

HPFDIS bit in the CONFIG0 register = 0.

0x6

R/W

000 38.695 Hz.

001 19.6375 Hz.

010 9.895 Hz.

011 4.9675 Hz.

100 2.49 Hz.

101 1.2475 Hz.

110 0.625 Hz.

111 0.3125 Hz.

[8:0]

RESERVED

Reserved.

0x0

0x4B0 EP_CFG

[15:13] NOLOAD_TMR

This register configures how many 4 kSPS samples

to evaluate the no load condition over.

0x0

R/W

000 64.

001 128.

010 256.

011 512.

100 1024.

101 2048.

110 4096.

111 Disable no load threshold.

[12:8]

RESERVED

Reserved.

0x0

PWR_SIGN_SEL

Selects whether the REVRPx bit follows the sign of

the total or fundamental reactive power.

0x0

R/W

0 Total reactive power.

1 Fundamental reactive power.

RESERVED

Reserved.

0x0

RD_RST_EN

Set this bit to enable the energy register read with

reset feature. If this bit is set, when one of the

xWATTHR, xVAHR, xVARHR and xFVARHR register is

read, it is reset and begins accumulating energy

from zero.

0x0

R/W

EGY_LD_ACCUM

If this bit = 0, the internal energy register is added

to the user accessible energy register. If the bit is

set, the internal energy register overwrites the

user accessible energy register when the EGYRDY

event occurs.

0x0

R/W

[3:2]

RESERVED

Reserved.

0x0

EGY_TMR_MODE

This bit determines whether energy is

accumulated based on the number of 4 kSPS

samples or zero crossing events configured in the

EGY_TIME register.

0x0

R/W

0 Accumulate energy based on 4 kSPS samples.

1 Accumulate energy based on the zero crossing

selected by the ZX_SEL bits in the ZX_LP_SEL

EGY_PWR_EN

Set this bit to enable the energy and power

accumulator, when the run bit is also set.

0x0

R/W

ADE9078 Datasheet(PDF) 105 Page - Analog Devices

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