TNETV1644ZDU6 datasheet(229/306 Pages) TI1

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PCLK

(Positive Edge Clocking)

PCLK

(Negative Edge Clocking)

VCTL(A)

A. VCTL = HSYNC and VSYNC

VPBECLK

LCD_FIELD

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 6-43. Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK(1) (see

Figure 6-24)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

tsu(VCTLV-PCLK)

Setup time, VCTL valid before PCLK edge

th(PCLK-VCTLV)

Hold time, VCTL valid after PCLK edge

tsu(VCTLV-VPBECLK)

Setup time, VCTL valid before VPBECLK rising edge

th(VPBECLK-VCTLV)

Hold time, VCTL valid after VPBECLK rising edge

tsu(FIELD-PCLK)

Setup time, LCD_FIELD valid before PCLK edge

5P(2)

th(PCLK-FIELD)

Hold time, LCD_FIELD valid after PCLK edge

5P(2)

tsu(FIELD-VPBECLK)

Setup time, LCD_FIELD valid before VPBECLK edge

5P(2)

th(VPBECLK-FIELD)

Hold time, LCD_FIELD valid after VPBECLK edge

5P(2)

(1)

PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising

edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.

(2)

P = 1/(VCLKIN clock frequency) in ns. VCLKIN is either PCLK or VPBECLK, whichever is used.

Figure 6-24. VPBE Input Timing With Respect to PCLK and VPBECLK

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