ST10F296 datasheet(161/346 Pages) STMICROELECTRONICS

161 / 346 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296E

Parallel ports

161/346

Figure 53.

Port 7 I/O and alternate functions

The structure of Port 7 differs from the other ports in the way the output latches are

connected to the internal bus and to the pin driver (see Figure 54 on page 161 and

Figure 55 on page 162).

Pins P7.3 to P7.0 (POUT3 to POUT0) XOR the alternate data output with the port latch

output. This allows alternate data to be used directly or inverted at the pin driver.

Pins P7.7 to P7.4 (CC31IO to CC28IO) combine internal bus data and alternate data output

before the port latch input.

Figure 54.

Block diagram of Port 7 pins 3 to 0

Port 7

Alternate function

General purpose input/output

P7.7

P7.6

P7.5

P7.4

P7.3

P7.2

P7.1

P7.0

CC31IO

CC30IO

CC29IO

CC28IO

POUT3

POUT2

POUT1

POUT0

Open-drain

latch

Write ODP7.y

Read ODP7.y

Direction

latch

Write DP7.y

Read DP7.y

MUX

Input

latch

Clock

P7.y/POUTy

Output

buffer

y = (3 to 0)

Port output

latch

Read P7.y

Write P7.y

Port data

output

XOR

Alternate

data

output

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 Datasheet(PDF) 161 Page - STMicroelectronics

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