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ST10F296 Datasheet(PDF) 239 Page - STMicroelectronics |
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ST10F296 Datasheet(HTML) 239 Page - STMicroelectronics |
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239 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E System reset 239/346 Figure 92. Port 0 bits latched into the different registers after reset RP0H Clock Port 4 logic Port 6 logic SYSCON BUSCON0 Internal control logic 76 2 P0L.7 P0L.7 7 9 Port 0 Bootstrap loader generator 10 9 EA/VSTBY 10 BTYP ALE CTLO BUS ACTO WR CFG BYT DIS RO MEN CKLKCFG SALSEL CSSEL WRC H.7 H.6 H.5 H.4 H.3 H.2 H.1 H.0 L.7 L.6 L.5 L.4 L.3 L.2 L.1 L.0 CKLKCFG SALSEL CSSEL WRC BUSTYP BSL Reserved ADP EMU Obsolete Product(s) - Obsolete Product(s) |
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