FEATURES:
• Optimized for 2.5V LVTTL
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 300 (max)
• High speed propagation delay < 1.8ns. (max)
• Up to 200MHz operation
• Very low CMOS power levels
• Hot insertable and over-voltage tolerant inputs
• 1:5 fanout buffer
• 2.5V VDD
• Available in TSSOP package
• For New Designs use functional replacement 8L30110

DESCRIPTION:
The 5T9050 2.5V single data rate (SDR) clock buffer is a single-ended input
to fi ve single-ended outputs buffer built on advanced metal CMOS technology.
The SDR clock buffer fanout from a single input to fi ve single-ended outputs
reduces the loading on the preceding driver and provides an effi cient clock
distribution network. Multiple power and grounds reduce noise.