FEATURES
• Nine differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
• Additive phase jitter, RMS: 0.17ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• Industrial Temperature information available upon request