Features
• Input clock frequency of 1 kHz to 170 MHz
• Output clock frequency of 500 kHz to 160 MHz
• Jitter attenuation of input clock provided by VCXO circuit.
Jitter transfer characteristics user configured through
selection of external loop filter components.
• 3:1 Input MUX for input reference clocks
• PLL lock status output
• PLL Clear function allows seamless synchronizing to an
altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
• VCXO-based clock generation offers very low jitter and
phase noise generation, even with a low frequency or
jittery input clock.
• 2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies (TCLK).
• Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
• 56 pin TSSOP package
• Single 3.3 V power supply
• 5 V tolerant inputs on ICLK0 and ICLK1