Core Features:
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- 0-32MHz
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-bit Timers
• One 16-bit Timer
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Low-Power Brown-out Reset (LPBOR)
• Programmable Watchdog Timer (WDT) up to
256s
• Programmable Code Protection