1FEATURES
2• Master/Slave Clock Selection in a Backplane
Application
• 125 MHz Operation (Typical)
• 100 ps Duty Cycle Distortion (Typical)
• 50 ps Channel to Channel Skew (Typical)
• 3.3V Power Supply Design
• Glitch-free Power on at CLKI/O Pins
• Low Power Design (20 mA @ 3.3V Static)
• Accepts Small Swing (300 mV Typical)
Differential Signal Levels
• Industrial Temperature Operating Range (-40°C
to +85°C)
• Available in 24-pin TSSOP Packaging

DESCRIPTION
The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver
is a one to six CMOS differential clock distribution
device utilizing Bus Low Voltage Differential Signaling
(BLVDS) technology. This clock distribution device is
designed for applications requiring ultra low power
dissipation, low noise, and high data rates. The
BLVDS side is a transceiver with a separate channel
acting as a return/source clock.
The DS92CK16 accepts LVDS (300 mV typical)
differential input levels, and translates them to 3V
CMOS output levels. An output enable pin OE , when
high, forces all CLKOUT pins high.
The device can be used as a source synchronous
driver. The selection of the source driving is
controlled by the CrdCLKIN and DE pins. This device
can be the master clock, driving the inputs of other
clock I/O pins in a multipoint environment. Easy
master/slave clock selection is achieved along a
backplane.