• LP-HCSL outputs; save 16 resistors compared to
standard HCSL outputs
• 53mW typical power consumption in PLL mode;
eliminates thermal concerns
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
• Spread Spectrum (SS) compatible; allows SS for EMI reduction
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• SMBus-selectable features; optimize signal integrity to
application:
• Slew rate for each output
• Differential output amplitude
• Pin/SMBus selectable PLL bandwidth and PLL Bypass; optimize PLL to application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface
not required for device control
• Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 48-pin 6 x 6 mm VFQFPN; minimal board space