• Twelve low skew, low additive jitter LVPECL outputs
• Two selectable, differential clock inputs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input (input select)
• Output skew: 33ps (maximum)
• Propagation delay: 550ps (maximum)
• Low additive phase jitter, RMS at fREF = 156.25MHz, VPP = 1V,
12kHz–20MHz: 60fs (maximum)
• Full 3.3V and 2.5V supply voltage
• Device current consumption (IEE): 131mA (maximum)
• Available in Lead-free (RoHS 6), 40-VFQFPN package
• -40°C to +85°C ambient operating temperature
• Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
• Supports PCI Express Gen1–5