Introduction
Field-programmable system chips (FPSCs) bring a whole new dimension to programmable logic: FPGA logic and an embedded system solution on a single device. Agere Systems Inc. has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer.

Embedded Core Features (Serial)
■ Implemented in an ORCA Series 4 FPGA.
■ Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer.
■ No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz—106 MHz clock, and a frame pulse.
■ High-speed interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
■ Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8 Gbits/s (full duplex).
■ HSI function uses Agere’s 850 Mbits/s serial interface core. Rates from 212 Mbits/s to 850 Mbits/s are supported directly (lower rates directly supported through decimation and interpolation).
■ LVDS I/Os compliant with EIA®-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes.
■ Low-power 1.5 V HSI core.
■ Low-power LVDS buffers.
■ Programmable STS-1, STS-3, and STS-12 framing.
■ Independent STS-1, STS-3, and STS-12 data streams per quad channels.
■ 8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic.
■ On-chip, phase-lock loop (PLL) clock meets B jitter tolerance specification of ITU-T recommendation G.958.
■ Powerdown option of HSI receiver on a per-channel basis.
■ Selectable 8B/10B coder/decoder or SONET scrambler/descrambler.
■ HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.
■ Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above rates.
■ In-band management and configuration through transport overhead extraction/insertion.
■ Supports transparent modes where either the only insertion is A1/A2 framing bytes, or no bytes are inserted.
■ Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks.
■ Built-in boundry scan (IEEE ®1149.1 JTAG).
■ FIFOs align incoming data across all eight channels (two groups of four channels or four groups of two channels) for both SONET scrambling and 8B/10B modes. Optional ability to bypass alignment FIFOs.
■ 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications. STS-192 and above rates are supported through multiple devices.
■ ORCA FPGA soft intellectual property core support for a variety of applications.
■ Programmable STM pointer mover bypass mode.
■ Programmable STM framer bypass mode.
■ Programmable CDR bypass mode (clocked LVDS high-speed interface).
■ Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels with redundancy on a single device.