FEATURES
• 1.8V power supply, 1.8V I/O power
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
   - CAS Latency ( 3 )
   - Burst Length ( 2, 4, 8 )
   - Burst Type (Sequential & Interleave)
   - Partial Self Refresh Type ( Full, 1/2, 1/4 array )
   - Internal Temperature Compensated Self Refresh
   - Driver strength ( 1, 1/2, 1/4, 1/8 )
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• LDM/UDM for write masking only.
• 7.8us auto refresh duty cycle.
• CSP package.