56F8345 Description

The 56F8345 is a member of the 56800E core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration  flexibility,  and  compact  program  code,  the  56F8345  is  well-suited  for  many applications. The 56F8345 includes many peripherals that are especially useful for motion control, smart  appliances,  steppers,  encoders,  tachometers,  limit  switches,  power  supply  and  control, automotive  control,  engine  management,  noise  suppression,  remote  utility  metering,  industrial control for power, lighting, and automation applications.

56F8345 Features

Digital Signal Processing Core

• Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture

• As many as 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

• Single-cycle 16 ×16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• Arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/EOnCE debug programming interface



Memory

• Harvard architecture permits as many as three simultaneous accesses to program and data memory

• Flash security protection feature

• On-chip memory, including a low-cost, high-volume Flash solution

— 128KB of Program Flash

— 4KB of Program RAM

— 8KB of Data Flash

— 8KB of Data RAM

— 8KB of Boot Flash

• EEPROM emulation capability