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K6R1016V1C Datasheet(PDF) 5 Page - Samsung semiconductor

Part # K6R1016V1C
Description  64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
PDF  11 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K6R1016V1C Datasheet(HTML) 5 Page - Samsung semiconductor

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K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
CMOS SRAM
Revision 3.3
- 5 -
October 2000
for AT&T
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R1016V1C-10
K6R1016V1C-12
K6R1016V1C-15
K6R1016V1C-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
10
-
12
-
15
-
20
-
ns
Chip Select to End of Write
tCW
7
-
8
-
9
-
10
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
7
-
8
-
9
-
10
-
ns
Write Pulse Width(OE High)
tWP
7
-
8
-
9
-
10
-
ns
Write Pulse Width(OE Low)
tWP1
10
-
12
-
15
-
20
-
ns
UB, LB Valid to End of Write
tBW
7
-
8
-
9
-
10
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
5
0
6
0
7
0
9
ns
Data to Write Time Overlap
tDW
5
-
6
-
7
-
8
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
3
-
3
-
3
-
3
-
ns
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R1016V1C-10
K6R1016V1C-12
K6R1016V1C-15
K6R1016V1C-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
10
-
12
-
15
-
20
-
ns
Address Access Time
tAA
-
10
-
12
-
15
-
20
ns
Chip Select to Output
tCO
-
10
-
12
-
15
-
20
ns
Output Enable to Valid Output
tOE
-
5
-
6
-
7
-
9
ns
UB, LB Access Time
tBA
-
5
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
3
-
ns
UB, LB Enable to Low-Z Output
tBLZ
0
-
0
-
0
-
0
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
5
0
6
-
7
-
9
ns
Output Disable to High-Z Output
tOHZ
0
5
0
6
-
7
-
9
ns
UB, LB Disable to High-Z Output
tBHZ
0
5
0
6
-
7
-
9
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
tPD
-
10
-
12
-
15
-
20
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL
tAA
tRC
tOH



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