3

8393CS-MCU Wireless-09/14

ATmega256/128/64RFR2

3 Overview

The ATmega256/128/64RFR2 is a low-power CMOS 8-bit microcontroller based on the

AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4

GHz ISM band.

By executing powerful instructions in a single clock cycle, the device achieves

throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

The radio transceiver provides high data rates from 250 kb/s up to 2 Mb/s, frame

handling, outstanding receiver sensitivity and high transmit output power enabling a

very robust wireless communication.

3.1 Block Diagram

Figure 3-1 Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working

registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Two

independent registers can be accessed with one single instruction executed in one

clock cycle. The resulting architecture is very code efficient while achieving throughputs

up to ten times faster than conventional CISC microcontrollers. The system includes

internal voltage regulation and an advanced power management. Distinguished by the

small leakage current it allows an extended operation time from battery.

The radio transceiver is a fully integrated ZigBee solution using a minimum number of

external components. It combines excellent RF performance with low cost, small size

and low current consumption. The radio transceiver includes a crystal stabilized

fractional-N synthesizer, transmitter and receiver, and full Direct Sequence Spread