SLG46110V datasheet(14/82 Pages) DIALOG

14 / 82 page

000-0046110-106

Page 13 of 81

SLG46110

6.0 Summary of Macrocell Function

6.1 I/O Pins

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Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)

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Open Drain Outputs

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Push Pull Outputs

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Analog I/O

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10 k

/100 k/1 Mpull-up/pull-down resistors

6.2 Connection Matrix

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Digital matrix for circuit connections based on user design

6.3 Analog Comparators (2 total)

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Selectable hysteresis 0 mV/25 mV/50 mV/200 mV

6.4 Voltage Reference

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Used for references on Analog Comparators

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Can also be driven to external pin (Pin 10)

6.5 Combinational Logic Look Up Tables (LUTs – 4 total)

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Two 2-bit Lookup Tables

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Two 3-bit Lookup Tables

6.6 Combination Function Macrocells (7 total)

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Two Selectable DFF/Latch or 2-bit LUTs

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Two Selectable DFF/Latch or 3-bit LUTs

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One Selectable Pipe Delay or 3-bit LUT

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One Selectable CNT/DLY or 4-bit LUT

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One Programmable Delay or Deglitch Filter

6.7 Delays/Counters (3 total)

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Three 8-bit delays/counters with external clock/reset: Range 1-255 clock cycles

6.8 Pipe Delay (Part of Combination Function Macrocell)

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8 stage / 2 output

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Two 1-8 stage selectable outputs.

6.9 Programmable Delay

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125 ns/250 ns/375 ns/500 ns @ 3.3 V

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Includes Edge Detection function

6.10 Additional Logic Functions (Part of Combination Function Macrocell)

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One Deglitch filter macrocell

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