DA6102 datasheet(4/82 Pages) DIALOG

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DA6102

6-Channel High Efficiency PMIC for 2-Cell Systems

Datasheet

Revision 2.1

28-Apr-2017

4 of 82

Figures

Figure 1: System Diagram..................................................................................................................... 2

Figure 2: Connection Diagram (Top View) ............................................................................................ 6

Figure 3: I

2C Timing............................................................................................................................. 17

Figure 4: Frequency vs Temperature .................................................................................................. 18

Figure 5: IQ_Standby vs VBATT ......................................................................................................... 18

Figure 6: LDO1 Load Regulation......................................................................................................... 18

Figure 7: LDO2 Load Regulation......................................................................................................... 18

Figure 8: Ch 1 Efficiency (Vout = 5.3 V) .............................................................................................. 19

Figure 9: Ch 2 Efficiency (Vout = 4.25 V) ............................................................................................ 19

Figure 10: Ch 3 Efficiency (Vout = 3.3 V) ............................................................................................ 19

Figure 11: Ch 4 Efficiency (Vout = 4.0 V) ............................................................................................ 19

Figure 12: Ch 1 Load Regulation ........................................................................................................ 19

Figure 13: Ch 2 Load Regulation ........................................................................................................ 19

Figure 14: Ch 3 Load Regulation ........................................................................................................ 20

Figure 15: Ch 4 Load Regulation ........................................................................................................ 20

Figure 16: Ch 1 Load Transient Response ......................................................................................... 20

Figure 17: Ch 2 Load Transient Response ......................................................................................... 20

Figure 18: Ch 3 Load Transient Response ......................................................................................... 20

Figure 19: Ch 4 Load Transient Response ......................................................................................... 20

Figure 20: CS1 Accuracy..................................................................................................................... 21

Figure 21: CS2 Accuracy..................................................................................................................... 21

Figure 22: CS3 Accuracy..................................................................................................................... 21

Figure 23: Example Start-up Sequence .............................................................................................. 21

Figure 24: Shutdown Sequence .......................................................................................................... 21

Figure 25: Typical Application Schematic ........................................................................................... 22

Figure 26: LDO1 and LDSW1 Architecture ......................................................................................... 24

Figure 27: LDO Start-upStart-up and LDSW1 Timing ......................................................................... 25

Figure 28: LDO2 and LDSW2 Architecture ......................................................................................... 26

Figure 29: Operating State Transitions ............................................................................................... 28

Figure 30: Sequencer, Enable, and FAULT logic................................................................................ 29

Figure 31: Sequencer Start-Up Example ............................................................................................ 30

Figure 32: Frequency Selection and Distribution ................................................................................ 33

Figure 33: OV and SC Fault Protection Example................................................................................ 35

Figure 34: CS1 Functional Diagram .................................................................................................... 41

Figure 35: PGOOD Function ............................................................................................................... 43

Figure 36: Short Circuit FAULT Logic ................................................................................................. 43

Figure 37: I

2C Start (S) and Stop (P)................................................................................................... 47

Figure 38: Single Write Command ...................................................................................................... 47

Figure 39: Consecutive Write Command ............................................................................................ 48

Figure 40: Single Read Command (Two Methods) ............................................................................. 48

Figure 41: Sequential Address Multiple Read Command ................................................................... 49

Figure 42: PCB Layout Guidelines ...................................................................................................... 51

Figure 43: Current Mode Loop Gain.................................................................................................... 76

Figure 44: Voltage Mode Loop Gain (Channel3) ................................................................................ 78

Figure 45: Package Outline Drawing................................................................................................... 80

Tables

Table 1: Pin Description ........................................................................................................................ 7

Table 2: Pin Type Definition .................................................................................................................. 9

Table 3: Absolute Maximum Ratings..................................................................................................... 9

Table 4: Recommended Operating Conditions ................................................................................... 10

Table 5: DC Characteristics................................................................................................................. 10

Table 6: AC Characteristics................................................................................................................. 16

Table 7: I

2C Timing Characteristics ..................................................................................................... 17

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