L9680 datasheet(51/277 Pages) STMICROELECTRONICS

51 / 277 page

DocID029257 Rev 1

51/277

L9680

Start-up and power control

276

Three internal reset signals are generated by the device:



POR

Power On Reset - This reset is asserted when a failure is detected in the internal

supplies or bandgap circuits. When active, all other resets are asserted.



WSM_RESET

Watchdog State Machine Reset - This reset is generated when the POR is active or

when a failure is detected in the VCC or VCORE supply.



SSM_RESET

System State Machine Reset - This reset is asserted when the POR or the

WSM_RESET are active, or when a failure is detected in either Watchdog state

machine, or again when the MCUFAULTB pin is active.

The RESET pin is the active-low signal driven on the output pin, and is an inverted form of

SSM_RESET.

The cause of the RESET activation is latched and reported into the Fault Status Register

FLTSR and cleared upon SPI reading.

The reset generated by the MCUFLT_ERR can be masked by the MCU_FLT_TEST test

mode signal. This allows verification of MCUFLT pin operation and, in turn, microcontroller

fault conditions without asserting a reset. The MCURST bit is still set whether in test mode

or not.

The reset logic shall be controlled as shown in the diagram below:

Figure 26. Reset control logic

L9680 Datasheet(PDF) 51 Page - STMicroelectronics