| Electronic Components Datasheet Search |
|
74LX1G02STR Datasheet(PDF) 1 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
74LX1G02STR Datasheet(HTML) 1 Page - STMicroelectronics |
|
1 / 10 page ![]() 1/10 October 2002 s 5V TOLERANT INPUTS s HIGH SPEED: tPD = 4.2ns (MAX.) at VCC =3V s LOW POWER DISSIPATION: ICC =1µA(MAX.) at TA =25°C s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL = 24mA (MIN) at VCC =3V s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 5.5V (1.2V Data Retention) s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LX1G02 is a low voltage CMOS SINGLE 2-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge. 74LX1G02 SINGLE 2-INPUT NOR GATE PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE T & R SOT23-5L 74LX1G02STR SOT323-5L 74LX1G02CTR SOT323-5L SOT23-5L |
Similar Part No. - 74LX1G02STR |
|
Similar Description - 74LX1G02STR |
|
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |