AD9874EB datasheet(16/40 Pages) AD

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REV. 0

–16–

AD9874

DOUT

CLKOUT

SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0

I15

Q15

Q14

CLKOUT

DOUT

SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC = 0

I15

Q15

Q14

RSSI0

ATTEN6

ATTN7

CLKOUT

DOUT

SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0

I15

Q15

Q14

CLKOUT

DOUT

SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0

SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 0, EAGC = 0: AS ABOVE, BUT FS IS LOW

IDLE (HIGH) BITS

START

BIT

START

BIT

STOP

BIT

STOP

BIT

START

BIT

HI-Z

I15

Q15

Figure 3a. SSI Timing for Several SSICRA Settings with 16-Bit I/Q Data

Table IV. Number of Bits per Frame for Different

SSICR Settings

Number of Bits

EAGC

EFS

AAGC

per Frame

0 (16-bit)

1 (24-bit)

*The number of bits per frame with embedded frame sync (EFS = 1) assume at

least 10 idle bits are desired.

The maximum SSIORD setting can be determined by the

following equation:

SSIORD

TRUNC Dec Factor

of Bits per Frame

≤

{(

) / (#

)}(1)

where TRUNC is the truncated integer value.

Table IV lists the number of bits within a frame for 16-bit and

24-bit output data formats for all of the different SSICR settings.

The decimation factor is determined by the contents of

An example helps illustrate how the maximum SSIORD setting

is determined. Suppose a user selects a decimation factor of 600

(Register 0x07, K = 0, M = 9) and prefers a 3-wire interface

with a dedicated frame sync (EFS = 0) containing 24-bit data

(DW = 1) with nonalternating embedded AGC data included

(EAGC = 1, AAGC = 0). Referring to Table IV, each frame will

consist of 64 data bits. Using Equation 1, the maximum

SSIORD setting is 9 (= TRUNC(600/64)). Thus, the user can

select any SSIORD setting between 1 and 9.

Figure 3a illustrates the output timing of the SSI port for several

SSI control register settings with 16-bit I/Q data, while Figure 3b

shows the associated timing parameters. Note, the same timing

relationship holds for 24-bit I/Q data, with the exception that I and

Qword lengths now become 24 bits. In the default mode of the

operation, data is shifted out on rising edges of CLKOUT after a

pulse equal to a clock period is output from the Frame Sync (FS)

Pin. As described above, the output data consists of a 16- or 24-bit

I sample followed by a 16- or 24-bit Q sample, plus two optional

bytes containing AGC and status information.

DOUT

I15

I14

CLKOUT

tCLK

tHI

tLOW

Figure 3b. Timing Parameters for SSI Timing*

*Timing parameters also apply to inverted CLKOUT or FS modes with t DV

relative to the falling edge of the CLK and/or FS.

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