NBC12430, NBC12430A

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The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless

explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable

of driving two series terminated 50

W transmission lines on the incident edge.

PIN FUNCTION DESCRIPTION

Pin Name

Function

Description

INPUTS

XTAL1, XTAL2

Crystal Inputs

These pins form an oscillator when connected to an external series−resonant

crystal.

S_LOAD*

CMOS/TTL Serial Latch Input

(Internal Pulldown Resistor)

This pin loads the configuration latches with the contents of the shift registers. The

latches will be transparent when this signal is HIGH; thus, the data must be stable

on the HIGH−to−LOW transition of S_LOAD for proper operation.

S_DATA*

CMOS/TTL Serial Data Input

(Internal Pulldown Resistor)

This pin acts as the data input to the serial configuration shift registers.

S_CLOCK*

CMOS/TTL Serial Clock Input

(Internal Pulldown Resistor)

This pin serves to clock the serial configuration shift registers. Data from S_DATA

is sampled on the rising edge.

P_LOAD**

CMOS/TTL Parallel Latch Input

(Internal Pullup Resistor)

This pin loads the configuration latches with the contents of the parallel inputs

.The latches will be transparent when this signal is LOW; therefore, the parallel

data must be stable on the LOW−to−HIGH transition of P_LOAD for proper opera-

tion.

M[8:0]**

CMOS/TTL PLL Loop Divider

Inputs (Internal Pullup Resistor)

These pins are used to configure the PLL loop divider. They are sampled on the

LOW−to−HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.

N[1:0]**

CMOS/TTL Output Divider Inputs

(Internal Pullup Resistor)

These pins are used to configure the output divider modulus. They are sampled

on the LOW−to−HIGH transition of P_LOAD.

OE**

CMOS/TTL Output Enable Input

(Internal Pullup Resistor)

Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of

FREF_EXT*

CMOS/TTL Input

(Internal Pulldown Resistor)

This pin can be used as the PLL Reference

XTAL_SEL**

CMOS/TTL Input

(Internal Pullup Resistor)

This pin selects between the crystal and the FREF_EXT source for the PLL refer-

ence signal. A HIGH selects the crystal input.

OUTPUTS

PECL Differential Outputs

These differential, positive−referenced ECL signals (PECL) are the outputs of the

synthesizer.

TEST

PECL Output

The function of this output is determined by the serial configuration bits T[2:0].

POWER

Positive Supply for the Logic

The positive supply for the internal logic and output buffer of the chip, and is con-

nected to +3.3 V or +5.0 V.

Positive Supply for the PLL

This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.

GND

Negative Power Supply

These pins are the negative supply for the chip and are normally all connected to

ground.

*

When left Open, these inputs will default LOW.

** When left Open, these inputs will default HIGH.