2 HARDWARE SOLUTION

No problems can occur when the device is in the reset state as long as the voltage has not

reached the minimum value at which the CPU performs. A simple level detection circuit which

forces the reset input low before reaching this critical point prevents any unwanted writing into

the EEPROM.

Figure 1. Reset Network

Reset Pin

Figure 2. Supply/ Reset graph

Vdd max.

Min operating voltage

Reset Pin

PREVENTION OF DATA CORRUPTION IN ST6 ON-CHIP EEPROM

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