TLE9255WLC datasheet(91/100 Pages) INFINEON

91 / 100 page

Data Sheet

Rev. 1.02 2018-02-02

TLE9255W

Electrical Characteristics

Logic Input CSN

“high” level input voltage

threshold

-0.5 x

VIO

0.7 x

VIO

V–

P_10.7.21

“low” level input voltage

threshold

0.3 x

VIO

0.4 x

VIO

-V

–

P_10.7.31

“high” level input current

-2.0

–

2.0

µA

VCSN = VIO,

pull-down;

P_10.7.33

“low” level input current

-200

–

-20

µA

VCSN =0 V;

P_10.7.34

Input capacitance

CIN

––

P_10.7.35

Logic Output: MISO

“high” level output current IMISO_H

–-

-1.0

VMISO = VIO -0.4 V;

P_10.7.8

“low” level output current

IMISO_L

–

VMISO =0.4 V;

P_10.7.9

Rise time

tMISO_R

–

80.0

30% - 70% of VIO,

CMISO = 100 pF;

P_10.7.10

Fall time

tMISO_F

–

80.0

70% - 30% of VIO,

CMISO = 100 pF;

P_10.7.11

Difference of rise and fall

time

|tMISO_R -

tMISO_F|

–

10.0

CMISO = 100 pF;

P_10.7.12

“tri-state” leakage current

IMISO_Tri

-10.0

–

10.0

µA

0 < VMISO < VIO;

P_10.7.13

“tri-state” Input capacitance CIN_MISO

––

P_10.7.14

SPI data timing1)

Clock “high” period

tSCLK_H

125

–

P_10.7.15

Clock “low” period

tSCLK_L

125

–

P_10.7.16

Clock “low” before CSN

“low”

tbef

125

–

P_10.7.17

CSN setup time

tlead_NM

–

µs

Normal-operating

Mode, Stand-by

Mode, Receive-

only Mode;

P_10.7.18

CSN setup time

tlead_SP

6.0

–

µs

Selective Wake

Sub-Mode,

Selective Sleep

Sub-Mode, Sleep

WUP Mode;

P_10.7.19

SCLK setup time

tlag

250

–

P_10.7.20

MOSI setup time

tMOSI_SU

–

P_10.7.22

Table 22

SPI (cont’d)

4.75 V < VCC < 5.25 V; 3.0 V < VIO < 5.5 V; 5.5V < VBAT < 40V; RL =60 Ω; -40 °C < TJ < 150 °C;

all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Unit

Note or

Test Condition

Number

Min.

Typ.

Max.

TLE9255WLC Datasheet(PDF) 91 Page - Infineon Technologies AG

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