HIP6021

FN4684 Rev 1.00

Page 8 of 15

March 8, 2005

Fault Protection

All four outputs are monitored and protected against extreme

overload. A sustained overload on any output or an over-

drives the FAULT/RT pin to VCC.

Figure 4 shows a simplified schematic of the fault logic. An

over-voltage detected on VSEN1 immediately sets the fault

latch. A sequence of three over-current fault signals also sets

the fault latch. The over-current latch is set dependent upon

the states of the over-current (OC), linear under-voltage (LUV)

and the soft-start signals. A window comparator monitors the

signal). An under-voltage on either linear output (VSEN2,

VSEN3, or VSEN4) is ignored until after the soft-start interval

increase without fault at start-up. Cycling the bias input voltage

fault latch.

Over-Voltage Protection

During operation, a short on the upper MOSFET of the PWM

exceeds the over-voltage threshold of 115% of DACOUT, the

over-voltage comparator trips to set the fault latch and turns

latch raises the FAULT/RT pin to VCC.

A separate over-voltage circuit provides protection during the

initial application of power. For voltages on the VCC pin below

the power-on reset (and above ~4V), the output level is

monitored for voltages above 1.3V. Should VSEN1 exceed this

level, the lower MOSFET, Q2 is driven on.

Over-Current Protection

All outputs are protected against excessive over-currents. The

PWM controller uses the upper MOSFET’s on-resistance,

output. All linear controllers monitor their respective VSEN pins

for under-voltage events to protect against excessive currents.

Figure 5 illustrates the over-current protection with an overload

on OUT1. The overload is applied at T0 and the current

CURRENT comparator trips when the voltage across Q1

This inhibits all outputs, discharges the soft-start capacitor

error amplifiers clamped by soft-start. With OUT1 still

overloaded, the inductor current increases to trip the over-

current comparator. Again, this inhibits all outputs, but the soft-

start voltage continues increasing to 4V before discharging.

The counter increments to 2. The soft-start cycle repeats at T3

and trips the over-current comparator. The SS pin voltage

increases to 4V at T4 and the counter increments to 3. This

sets the fault latch to disable the converter. The fault is

reported on the FAULT/RT pin.

The linear controllers operate in the same way as the PWM in

response to over-current faults. The differentiating factor for

the linear controllers is that they monitor the VSEN pins for

under-voltage events. Should excessive currents cause the

voltage at the VSEN pins to fall below the linear under-

voltage threshold, the LUV signal sets the over-current latch if

charge interval allows the linear outputs to build above the

under-voltage threshold during normal operation. Cycling the

bias input power off then on resets the counter and the fault

latch.

the PWM converter. As shown in Figure 6, the internal 200

A

FIGURE 3. SOFT-START INTERVAL

0V

0V

0V

TIME

PGOOD

SOFT-START

(1V/DIV)

OUTPUT

(0.5V/DIV)

VOLTAGES

T1

T2

T3

T0

T4

FAULT

LATCH

S

R

Q

POR

COUNTER

OC1

OV

LUV

+

-

+

-

0.15V

4V

SS

VCC

FAULT

R

FIGURE 4. FAULT LOGIC - SIMPLIFIED SCHEMATIC

UP

OVER-

CURRENT

LATCH

INHIBIT

S

R

Q