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EL4511 Datasheet(PDF) 21 Page - Renesas Technology Corp |
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EL4511 Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 24 page ![]() EL4511 FN7009 Rev 8.00 Page 21 of 24 November 12, 2010 TABLE 3. MODE CONTROL TRUTH TABLE (see also Table 2 for hardware over-ride) MODE CTRL EnTri Level EnBi Level EnHin Vin TriLevel Priority Hin Priority HinVin Only Reg 1 b5 b4 b3 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 EnTriLevel, EnBiLevel and EnHinVin; these enable tri-level sync detection, two-level sync detection and separate H/V (VGA) sync detection, respectively. Other signals used to prioritize tri-level syncs (TriLevPriority), separate H/V (Hin Priority), or to only allow signals from HIN/VERTIN (HinVinOnly). TABLE 4. ACQUISITION CONTROL SIGNALS REGISTER BIT SIGNAL NAME DESCRIPTION 8 3 En50Slice 1 = Sample and Hold front end is in use 8 1 Progressive 1 = Progressive scan detected 8 0 Tri-Level Detected 1 = Tri-Level syncs detected 9 5 ENLEVEL BLANKING 1 = VLEVEL is available when system is not locked 9 4 ENLEVEL 1 = Disable VLEVEL Output 9 2 ENALOS 1 = Analog loss of signal not used in lock indication. 14 5 SYNCLOCK Same information as SYNCLOCK pin 3 16 4 RateLocked Line rate is locked 16 3 ALOS Sync Amplitude is below minimum TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS REGISTER NUMBER REGISTER BIT SIGNAL NAME TYPE RESET VALUE DESCRIPTION AND COMMENTS 1 General Control Reg 1 R/W 00h 7 General Reset 0 Software reset. Does not affect serial interface. 6 AlwaysEnOutputs 0 Overrides internal qualification of outputs. 5:3 ModeCtrl 0 Sync acquisition. Selects input signal. See Table 3. 2 General Control Reg 2 R/W 10h 5 Select Fixed Slicing (no S/H) 0 Necessary for SECAM. May be useful for VCRs. 4 FILTER_ENABLED 1 Set Hi to include digital filter on horizontal input. 1 OE_MODE 0 Set Hi for Odd/Even changes on rising edge of vertical. 3VBLANK Control Reg 1 R/W 90h 7 EnVBlank 1 Enables vertical blank interval detection algorithm. 6:0 VSTPlusBP 10h Number of lines after vertical sync time. 4VBLANK & Polarity Ctrl R/W 4Fh 7:4 VFrontPorch 4h Number of lines before vertical sync time. 3 DefaultHPolarity 1 HIN polarity on reset if EnHpolarityDet = Lo. 2 DefaultVPolarity 1 VERTIN polarity on reset and if EnVpolarityDet = Lo. 1 EnHPolarityDet 1 Allows EL4511 to detect and set polarity on HIN. 0 EnVPolarityDet 1 Allows EL4511 to detect and set polarity on VERTIN. 6 Oscillator Control 2 R/W 22h 7:6 CMuxCtrl <1:0> 0 Multiplexes clock onto VBLANK or Odd/Even. See Table 1. 7VBLANK O/P Reg 1 R Only valid if VBLANK circuit is enabled 7:0 LinesPerFrame <7:0> - Least significant byte of lines per frame count. 8VBLANK O/P Reg 2 & Misc R 80h |
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