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AT89C51ED2-RDTIM Datasheet(PDF) 123 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM Datasheet(HTML) 123 Page - ATMEL Corporation |
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123 / 137 page  123 AT89C51RD2/ED2 4235E–8051–04/04 External Data Memory Write Cycle External Data Memory Read Cycle Serial Port Timing - Shift Register Mode Table 83. Symbol Description T QVWH T LLAX ALE PSEN WR PORT 0 PORT 2 A0-A7 DATA OUT ADDRESS OR SFR-P2 TAVWL TLLWL TQVWX ADDRESS A8-A15 OR SFR P2 TWHQX TWHLH TWLWH ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 TAVWL TLLWL TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDZ TWHLH TRLRH TLLDV TRHDX TLLAX TAVDV Symbol Parameter T XLXL Serial port clock cycle time T QVHX Output data set-up to clock rising edge T XHQX Output data hold after clock rising edge T XHDX Input data hold after clock rising edge T XHDV Clock rising edge to input data valid |
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