ZL2103ALAF datasheet(13/28 Pages) RENESAS

13 / 28 page

ZL2103

FN6966 Rev 5.00

Page 13 of 28

May 3, 2011

Power Conversion Functional

Description

Internal Bias Regulators and Input Supply

Connections

The ZL2103 employs three internal low dropout (LDO) regulators

to supply bias voltages for internal circuitry, allowing it to operate

from a single input supply. The internal bias regulators are as

follows:

• VR: The VR LDO provides a regulated 7V bias supply for the

high-side MOSFET driver circuit. It is powered from the VDDS

pin and supplies bias current internally. A 4.7µF filter capacitor

is required at the VR pin. The VDDS pin directly supplies the

low-side MOSFET driver circuit.

• VRA: The VRA LDO provides a regulated 5V bias supply for the

current sense circuit and other analog circuitry. It is powered

from the VDDS pin and supplies bias current internally. A

4.7µF filter capacitor is required at the VRA pin.

• V2P5:The V2P5 LDO provides a regulated 2.5V bias supply for

the main controller circuitry. It is powered from the VRA LDO

and supplies bias current internally. A 10µF filter capacitor is

required at the V2P5 pin.

When the input supply (VDDS) is higher than 7.5V, the VR and

VRA pins should not be connected to any other pins. These pins

should only have a filter capacitor attached. Due to the dropout

voltage associated with the VR and VRA bias regulators, the

VDDS pin must be connected to these pins for designs operating

from a supply below 7.5V. Figure 13 illustrates the required

connections for all cases.

Note: The internal bias regulators, VR and VRA, are not designed

to be outputs for powering other circuitry. Do not attach external

loads to any of these pins. Only the multi-mode pins may be

connected to the V2P5 pin for logic HIGH settings.

High-side Driver Boost Circuit

The gate drive voltage for the high-side MOSFET driver is

generated by a floating bootstrap capacitor, CB (see Figure 9).

When the lower MOSFET (QL) is turned on, the SW node is pulled

to ground and the capacitor is charged from the internal VR bias

regulator through diode DB. When QL turns off and the upper

MOSFET (QH) turns on, the SW node is pulled up to VDDP and the

voltage on the bootstrap capacitor is boosted approximately 6.5V

above VDDP to provide the necessary voltage to power the high-

side driver. An internal Schottky diode is used with CB to help

maximize the high-side drive supply voltage.

Output Voltage Selection

The output voltage may be set to any voltage between 0.6V and

5.0V provided that the input voltage is higher than the desired

output voltage by an amount sufficient to prevent the device

from exceeding its maximum duty cycle specification. Using the

pin-strap method, VOUT can be set to one of three standard

voltages as shown in Table 2.

7.5V < VIN≤ 14V

4.5V ≤ VIN ≤ 5.5V 5.5V < VIN≤ 7.5V

VRA

VDDS

VIN

VDDS

VRA

VIN

VDDS

VRA

VIN

FIGURE 13. INPUT SUPPLY CONNECTIONS

TABLE 2. PIN-STRAP OUTPUT VOLTAGE SETTINGS

VSET

VOUT

LOW

1.2V

OPEN

1.5V

HIGH

3.3V

TABLE 3. ZL2103 START-UP SEQUENCE

STEP #

STEP NAME

DESCRIPTION

TIME DURATION

Power Applied

Input voltage is applied to the ZL2103’s VDD pins (VDDP and VDDS).

Depends on input supply ramp

time

Internal Memory Check

The device will check for values stored in its internal memory. This step

is also performed after a Restore command.

Approx 5ms to 10ms (device will

ignore an enable signal or PMBus

traffic during this period)

Multi-mode Pin Check

The device loads values configured by the multi-mode pins.

Device Ready

The device is ready to accept an enable signal.

Pre-ramp Delay

The device requires approximately 2ms following an enable signal and

prior to ramping its output. Additional pre-ramp delay may be

configured using the SS pin.

Approximately 2ms

ZL2103ALAF Datasheet(PDF) 13 Page - Renesas Technology Corp

ZL2103ALAF Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL