M41ST95W datasheet(14/35 Pages) STMICROELECTRONICS

14 / 35 page

M41ST95Y*, M41ST95W

14/35

Figure 13. WRITE Mode Sequence

Data Retention Mode

With valid VCC applied, the M41ST95Y/W can be

accessed as described above with READ or

WRITE Cycles. Should the supply voltage decay,

the M41ST95Y/W will automatically deselect,

write protecting itself (and any external SRAM)

when

VCC

falls

between

VPFD(max)

and

VPFD(min). This is accomplished by internally in-

hibiting access to the clock registers. At this time,

the Reset pin (RST) is driven active and will re-

main active until VCC returns to nominal levels. Ex-

ternal RAM access is inhibited in a similar manner

by forcing ECON to a high level. This level is within

0.2 volts of the VBAT. ECON will remain at this level

as long as VCC remains at an out-of-tolerance con-

dition. When VCC falls below the Battery Back-up

Switchover Voltage (VSO), power input is switched

from the VCC pin to the SNAPHAT

® battery, and

the clock registers and external SRAM are main-

tained from the attached battery supply.

All outputs become high impedance. The VOUT pin

is capable of supplying 100 µA of current to the at-

tached memory with less than 0.3 volts drop under

this condition. On power up, when VCC returns to

a nominal value, write protection continues for

tREC by inhibiting ECON. The RST signal also re-

mains

active

during

this

time

(see

Figure

21., page 28).

Note: Most low power SRAMs on the market to-

day can be used with the M41ST95Y/W RTC SU-

PERVISOR. There are, however some criteria

which should be used in making the final choice of

an SRAM to use.

The SRAM must be designed in a way where the

chip enable input disables all other inputs to the

SRAM. This allows inputs to the M41ST95Y/W

and SRAMs to be “Don’t Care” once VCC falls be-

low VPFD(min). The SRAM should also guarantee

data retention down to VCC = 2.0 volts. The chip

enable access time must be sufficient to meet the

system needs with the chip enable output propa-

gation delays included. If the SRAM includes a

second chip enable pin (E2), this pin should be

tied to VOUT.

If data retention lifetime is a critical parameter for

the system, it is important to review the data reten-

tion

current

specifications

for

the

particular

SRAMs being evaluated. Most SRAMs specify a

data retention current at 3.0 volts. Manufacturers

generally specify a typical condition for room tem-

perature along with a worst case condition (gener-

ally at elevated temperatures). The system level

requirements will determine the choice of which

value to use. The data retention current value of

the SRAMs can then be added to the IBAT value of

the M41ST95Y/W to determine the total current re-

quirements for data retention. The available bat-

tery capacity for the SNAPHAT® of your choice

can then be divided by this current to determine

the amount of data retention available (see 20).

For a further more detailed review of lifetime calcu-

lations, please see Application Note AN1012.

SCL

SDI

SDO

HIGH IMPEDANCE

DATA BYTE

7 BIT ADDR

W/R BIT

MSB

AI04636

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