SSM4321

Data Sheet

Rev. 0 | Page 18 of 24

TIMING DIAGRAMS, TDM MODE

TDM Mode, One Device

SLOT pin is tied to IOVDD.

64 BCLKs

CURRENT

VOLTAGE

16 BCLKs

PVDD

16 BCLKs

8 BCLKs

BCLK_TDM

FSYNC_TDM

SDATAO

Figure 39. TDM Mode, One Device

TDM Mode, Two Devices

IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open.

BCLK_TDM

FSYNC_TDM

SDATAO

CURRENT, IC 1

VOLTAGE, IC 1

PVDD, IC 1

16 BCLKs

16 BCLKs

8 BCLKs

64 BCLKs

CURRENT, IC 2

VOLTAGE, IC 2

PVDD, IC 2

16 BCLKs

16 BCLKs

8 BCLKs

64 BCLKs

128 BCLKs

Figure 40. TDM Mode, Two Devices

TDM Mode, Three Devices

IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open; IC 3: SLOT pin is tied to GND.

BCLK_TDM

FSYNC_TDM

SDATAO

CURRENT, IC 1 VOLTAGE, IC 1 PVDD, IC 1

16 BCLKs

16 BCLKs

8 BCLKs

64 BCLKs

CURRENT, IC 2 VOLTAGE, IC 2 PVDD, IC 2

16 BCLKs

16 BCLKs

8 BCLKs

64 BCLKs

192 BCLKs

64 BCLKs

CURRENT, IC 3 VOLTAGE, IC 3 PVDD, IC 3

16 BCLKs

16 BCLKs

8 BCLKs

Figure 41. TDM Mode, Three Devices

Left justified output mode: SLOT pin is tied to IOVDD through a 47 kΩ resistor.

64 BCLKs

VOLTAGE

VOLTAGE

16 BCLKs

16 BCLKs

CURRENT

CURRENT

16 BCLKs

16 BCLKs

8 BCLKs

8 BCLKs

PVDD

PVDD

BCLK_I2S

LRCLK_I2S

SDATAO LJ