SC68C752B datasheet(13/49 Pages) PHILIPS

13 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

13 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.4 Reset

Table 5 summarizes the state of register after reset.

Remark: Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the

top-level reset signal RESET, that is, they hold their initialization values during reset.

Table 6 summarizes the state of registers after reset.

Table 5:

Reset control

Reset state

Interrupt Enable Register

RESET

all bits cleared

Interrupt Identiﬁcation Register

RESET

bit 0 is set; all other bits cleared

FIFO Control Register

RESET

all bits cleared

Line Control Register

RESET

reset to 0001 1101 (1Dh)

Modem Control Register

RESET

all bits cleared

Line Status Register

RESET

bits 5 and 6 set; all other bits cleared

Modem Status Register

RESET

bits 0 to 3 cleared; bits 4 to 7 input signals

Enhanced Feature Register

RESET

all bits cleared

Receiver Holding Register

RESET

pointer logic cleared

Transmitter Holding Register

RESET

pointer logic cleared

Transmission Control Register

RESET

all bits cleared

Trigger Level Register

RESET

all bits cleared

Table 6:

Signal RESET functions

Signal

Reset control

Reset state

RESET

HIGH

RTS

RESET

HIGH

DTR

RESET

HIGH

RXRDY

RESET

HIGH

TXRDY

RESET

LOW

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