SP6139 datasheet(6/13 Pages) SIPEX

6 / 13 page

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

THEORY OF OPERATION

zero response is required, then compensation

can be a simple as an RC to ground. If a more

complex compensation is required, then the

amplifier has enough bandwidth (45

° at 4 MHz)

and enough gain (60dB) to run Type III compen-

sation schemes with adequate gain and phase

margins at cross over frequencies greater than

50kHz.

The common mode output of the error amplifier

is 0.9V to 2.2V. Therefore, the PWM voltage

ramp has been set between 1.1V and 2.2V to

ensure proper 0% to 100% duty cycle capability.

The voltage loop also includes two other very

important features. One is an asynchronous start

up mode. Basically, the GL driver can not turn

on unless the GH driver has attempted to turn on

or the SS pin has exceeded 1.7V. This feature

prevents the controller from “dragging down”

the output voltage during startup or in fault

modes. The second feature is a 100% duty cycle

timeout that ensures synchronized refreshing of

the BST capacitor at very high duty ratios. In the

event that the GH driver is on for 20 continuous

clock cycles, a reset is given to the PWM flip

flop half way through the 21st cycle. This forces

GL to rise for the remainder of the cycle, in turn

refreshing the BST capacitor.

Gate Drivers

The SP6139 contains a pair of powerful 2

Ω

SOURCE and 1.5

Ω SINK drivers. These state

of the art drivers are designed to drive external

NFETs capable of handling up to 30A. Rise,

fall, and non-overlap times have all been minized

to achieve maximum efficiency. All drive pins

GH, GL & SWN are monitored continuously to

ensure that only one external NFET is ever on at

any given time.

90%

10%

RISE TIME

NON-OVERLAP

FALL TIME

90%

10%

GH(GL)

GL(GH)

GATE DRIVER TEST CONDITIONS

V(BST)

Voltage

V(VCC)

V(SWN)

Voltage

V(VIN)

-0V

-V(Diode) V

V(VIN)+V(VCC)

BST

Voltage

V(VCC)

TIME

SWN

Voltage

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