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STV0684 Datasheet(PDF) 30 Page - STMicroelectronics |
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STV0684 Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 49 page  Electrical Characteristics STV0684 30/49 Note: 1 The SDRAM interface is designed to operate with SDRAM devices which are compliant with the Intel SDRAM Specification Revision 1.7 November 1999. Speed grades 66, 100 and 133MHz are compatible. 2 Above timing assumes 20pF load per pad. Table 9: SDRAM timing Symbol Min Typ Max Units tCK 41.67 ns tCH tCK/2 - (tCK*0.0345) tCK/2 tCK/2 + (tCK*0.0345) ns tCL tCK/2 - (tCK*0.0345) tCK/2 tCK/2 + (tCK*0.0345) ns tAC 24.8 ns tOH 0 ns tCMS 20.3 ns tCMH 20 ns tAS 20.7 ns tDS 20.1 ns tDH 21.8 ns tRCD 1 tCK tRAS 2 tCK tRC 4 tCK tRP 2 tCK tRRD 1 2 tCK tah 19.8 ns 1. tRRD = Row active to row active delay |
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