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LTC6953 Datasheet(PDF) 5 Page - Analog Devices |
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LTC6953 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 56 page  LTC6953 5 Rev 0 For more information www.analog.com Preliminary Technical Data Advance Product Information Subject to Change Rev PrA ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified (Note 2). All voltages are with respect to GND. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Capacitance Differential 1.0 pF CMOS SYNC/SYSREF Request Input (EZS_SRQ+ Only) High-Level Input Voltage EZS_SRQ– Tied to GND l 1.3 V Low-Level Input Voltage EZS_SRQ– Tied to GND l 0.6 V Input Voltage Hysteresis EZS_SRQ– Tied to GND 200 mV Input Current EZS_SRQ– Tied to GND l ±1 µA Differential SYNC/SYSREF Request Inputs (EZS_SRQ+ and EZS_SRQ–) Input Signal Level l 0.5 0.8 2.7 VP-P Self-Bias Voltage l 1.8 2.1 2.4 V Input Common Mode Voltage 800mVP-P Differential Input 1.5 3.0 V Input Resistance Differential 53 kΩ Input Capacitance Differential 1 pF Digital Pin Specifications VIH High-Level Input Voltage CS, SDI, SCLK, SD l 1.55 V VIL Low-Level Input Voltage CS, SDI, SCLK, SD l 0.8 V VIHYS Input Voltage Hysteresis CS, SDI, SCLK, SD 250 mV Input Current CS, SDI, SCLK, SD l ±1 µA IOH High-Level Output Current SDO and STAT, VOH = VD+ – 400mV l –3.3 –1.9 mA IOL Low-Level Output Current SDO and STAT, VOL = 400mV l 2.0 3.4 mA SDO Hi-Z Current l ±1 µA Digital Timing Specifications tCKH SCLK High Time l 25 ns tCKL SCLK Low Time l 25 ns tCSS CS Setup Time l 10 ns tCSH CS High Time l 10 ns tCS SDI to SCLK Setup Time l 6 ns tCH SDI to SCLK Hold Time l 6 ns tDO SCLK to SDO Time To VIH/VIL/Hi-Z with 30pF Load l 16 ns EZS_SRQ Timing Specifications tSRQH EZS_SRQ High Time l 1 ms tSRQL EZS_SRQ Low Time l 1 ms EZS_SRQ Skew, Part to Part SRQMD = 0, PARSYNC = 0 10 µs Output Dividers (M0, M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10) Mx Output Divider Range (x = 0 to 10) Mx = P × 2N, Where P = 1 to 32 All Integers, N = 0 to 7 l 1 4096 counts DDELx Output Digital Delay (x = 0 to 10) ½ Input Cycles (Note 3) l 0 4095 ½ cycles |
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