8

©2016 Integrated Device Technology, Inc.

Revison C, November 2, 2016

8V41N012 Datasheet

Table 6. Input Frequency Characteristics,

AC Electrical Characteristics

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the

datasheet.

NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express

Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.

NOTE 4: This parameter is guaranteed by characterization. Not tested in production.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input

Frequency

CLK, nCLK

25

MHz

XTAL_IN,

XTAL_OUT

25

MHz

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

PCIe Industry

Specification

Units

(PCIe Gen 1)

Phase Jitter

Peak-to-Peak;

NOTE 1, 4

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

6.97

11.18

86

ps

(PCIe Gen 2)

Phase Jitter

RMS; NOTE 2, 4

ƒ = 100MHz, 25MHz Crystal Input

High Band: 1.5MHz - Nyquist

(clock frequency/2)

0.70

1.84

3.10

ps

(PCIe Gen 2)

Phase Jitter

RMS; NOTE 2, 4

ƒ = 100MHz, 25MHz Crystal Input

Low Band: 10kHz - 1.5MHz

0.03

0.07

3.0

ps

(PCIe Gen 3)

Phase Jitter

RMS; NOTE 3, 4

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

0.16

0.49

0.8

ps