M58WR032FT datasheet(68/86 Pages) STMICROELECTRONICS

68 / 86 page

M58WR032FT, M58WR032FB

68/86

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

2. Bank Regions. There are two Bank Regions, see Table 28. and Table 29.

(P+35)h = 6Eh

03h

(P+3D)h = 76h

03h

Bank Region 2 (Erase Block Type 1): Page mode and

synchronous mode capabilities (defined in table 10)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+36)h = 6Fh

07h

Bank Region 2 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

(P+37)h = 70h

00h

(P+38)h = 71h

20h

(P+39)h = 72h

00h

(P+3A)h = 73h

64h

Bank Region 2 (Erase Block Type 2)

Minimum block erase cycles × 1000

(P+3B)h = 74h

00h

(P+3C)h = 75h

01h

Bank Region 2 (Erase Block Type 2): BIts per cell, internal

ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

(P+3D)h = 76h

03h

Bank Region 2 (Erase Block Type 2): Page mode and

synchronous mode capabilities (defined in table 10)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+3E)h = 77h

Feature Space definitions

(P+3F)h = 78h

Reserved

M58WR032FT (top)

M58WR032FB (bottom)

Description

Offset

Data

Offset

Data

M58WR032FT Datasheet(PDF) 68 Page - STMicroelectronics

M58WR032FT Datasheet(HTML) 68 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL