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MSM548262-70JS Datasheet(PDF) 1 Page - OKI electronic componets |
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MSM548262-70JS Datasheet(HTML) 1 Page - OKI electronic componets |
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1 / 37 page  ¡ Semiconductor MSM548262 1/37 ¡ Semiconductor MSM548262 262,144-Word ¥ 8-Bit Multiport DRAM DESCRIPTION The MSM548262 is a 2-Mbit CMOS multiport DRAM composed of a 262,144-word by 8-bit dynamic RAM, and a 512-word by 8-bit SAM. Its RAM and SAM operate independently and asynchronously. It supports three types of operations: random access to RAM port, high speed serial access to SAM port, and bidirectional transfer of data between any selected row in the RAM port and the SAM port. In addition to the conventional multiport DRAM operating modes, the MSM548262 features block write, flash write functions on the RAM port and a split data transfer capability on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flip- flops. FEATURES • Single power supply: 5 V ±10% • Full TTL compatibility • Multiport organization RAM : 256K word ¥ 8 bits SAM : 512 word ¥ 8 bits • Fast page mode • Write per bit • Masked flash write • Masked block write • Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM548262-xxJS) 44/40-pin 400 mil plastic TSOP (Type II)(TSOPII44/40-P-400-0.80-K)(Product : MSM548262-xxTS-K) xx indicates speed rank. PRODUCT FAMILY • RAS only refresh • CAS before RAS refresh • Hidden refresh • Serial read/write • 512 tap location • Bidirectional data transfer • Split transfer • Masked write transfer • Refresh: 512 cycles/8 ms Access Time Cycle Time Power Dissipation RAM RAM Operating Standby SAM SAM 60 ns 120 ns 140 mA 8 mA 17 ns 22 ns 70 ns 140 ns 130 mA 8 mA 17 ns 22 ns 80 ns 150 ns 120 mA 8 mA 20 ns 25 ns Family MSM548262-60 MSM548262-70 MSM548262-80 E2L0016-17-Y1 This version: Jan. 1998 Previous version: Dec. 1996 |
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