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CY22K7
3
Notes:
1.
All control pins have internal pull-ups of 56K including: USB/IO, TEST, SPREAD, PWR_DWN, CPU_STOP, PCI_STOP.
2.
Part will go into test mode if three rising edges come on PCI_STOP while XTALIN is held low.
3.
Part will consume more shutdown current if external pull-ups are connected on latched input/outputs during power-down.
4.
TCLK/4 if Select = 0; TCLK/8 if Select = 1.
29
SPREAD
IN
Enables spread spectrum when LOW
30
PWR_DWN[3]
IN
Power-down when LOW, removes power from internal logic
31
CPU_STOP
IN
Stops CPU clocks when LOW
32
PCI_STOP[2]
IN
Stops PCI clocks when LOW
45
VDDSDRAM
PWR
Power for SDRAM_OUT
47
VSSSDRAM
PWR
Ground for SDRAM_OUT
46
SDRAM_OUT
OUT
CPU reference clock for SDRAM zero delay buffer
38, 41
VSSCPU
PWR
Ground for CPU outputs shorted to SDRAM ground
36, 39, 42
CPUCLKT[0:2]
OUT
“True” clocks of differential pair for CPU and host clock outputs
37, 40, 43
CPUCLKC[0:2]
OUT
“Complementary” clocks of differential pair for CPU and host clock outputs
35, 44
RESERVED
−
Reserved for future CPU power rail
Function Table
TEST
FS1
FS0
CPUCLK
SDRAM_OUT
PCICLK
PCICLK_F
AGP
USB/IO
REF
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
1
50
25
50
48/24
14.318
0
1
0
66
33
66
48/24
14.318
0
1
1
TCLK/2
TCLK/6
TCLK/3
TCLK/4[4]
TCLK
1
0
0
90
30
60
48/24
14.318
1
0
1
133
33.3
66.6
48/24
14.318
1
1
0
120
30
60
48/24
14.318
1
1
1
100
33.3
66.6
48/24
14.318
Pin Summary[1] (continued)
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Power Management Modes
PWR_DWN
CPU_STOP
PCI_
STOP
CPU+
CPU-
PCICLK
PCICLK_
F
Other
Clocks
Oscillator
PLLs
0
X
X
Low
High
Low
Low
Low
Off
Off
1
0
0
Low
High
Low
Running
Running
Running
Running
1
0
1
Low
High
Running
Running
Running
Running
Running
1
1
0
Running
Running
Low
Running
Running
Running
Running
1
1
1
Running
Running
Running
Running
Running
Running
Running
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