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PIFE32251B-R47MS Datasheet(PDF) 46 Page - Texas Instruments |
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PIFE32251B-R47MS Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 96 page  S0 SLP_S4B SLP_S0B VTT BUCK1 (VNN) S0 BUCK2 (VCCGI) BUCK3 (VCCRAM) SLP_S3B 0 V 1.05 V 0 V 0 V PCH_PWROK S3 T8 1.8 V VID ˜ 100 µs ˜ 5 ms SET VID by Host SWB1_2 (2) (1) LPDDR3 and LPDDR4 (2) DDR3L SWB1_2 (V1P8U) (1) 46 TPS65094 SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TPS65094 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated 6.3.5.4 S0 to S3 Entry and Exit Assertion of SLP_S3B (H → L) triggers S3 entry. Deassertion of SLP_S3B causes S3 exit and S0 entry as depicted in Figure 6-10. On S3 exit, BUCK1–BUCK3 behave exactly the same way as they do on S0iX exit, which is explained in Section 6.3.5.3, Connected Standby Entry and Exit. Figure 6-10. S3 Entry and Exit Sequence |
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