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FS511-PI Datasheet(PDF) 12 Page - Fortune Semiconductor Corp.

Part # FS511-PI
Description  18-bit ADC with 1 low noise OPAMP
PDF  18 Pages
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Manufacturer  FORTUNE [Fortune Semiconductor Corp.]
Direct Link  https://www.ic-fortune.com/eng/index.asp
Logo FORTUNE - Fortune Semiconductor Corp.

FS511-PI Datasheet(HTML) 12 Page - Fortune Semiconductor Corp.

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The symbolic diagram of the delta-sigma ADC is shown as above. It consists of an analog subtractor, an
integrator, a comparator, a 1-bit digital-to-analog converter (DAC), and a low-pass digital filter. The analog
signals are continuously sampled and are subtracted by the expected voltage. The difference of the signals is
fed into the integrator, and then the signal is compared with a reference voltage to find a digital output. This
digital output is converted by the 1-bit DAC to become an analog signal (+Vref or -Vref) and then negatively fed
back into the integrator. Due to the infinitive DC gain of the integrator, if the change of the input signal is much
slower than the sampling speed, the average voltage obtained by the delta-sigma modulator will be very close
to the input signal. In some resolution they can be treated to be the same, therefore, the 1-bit output data from
the comparator are equivalent to the  Vref analog signal values. The digital filter then decimates the 1-bit data
to get a very high resolution digital code.
ENAD(ADG<7>) is the enable control signal for the ADC. It is 1 to enable the ADC; it is 0 to turn off the ADC
and can save power.
11..3.1.
Gain Stage Setting
There are four different gain paths to the input of the FS511 ADC, and they are controlled by control
register ADG[3:0]. Two different gain paths control the input reference voltage, and they are controlled by
control register ADG[5:4]. The gains shown here are not accurate. The accurate gains can be found by careful
calibration.
0.5
0.5
0.25
0.1
Vin
(IN+, IN-)
ADG[0]
ADG[1]
ADG[2]
ADG[3]
To ADC
signal
input
1.0
0.25
Vref (VR+, VR-)
ADG[4]
ADG[5]
To ADC
reference
input
Diagram of FS511Gain Stage Setting
By proper selection of the gain paths, this ADC can be applied to the optimum dynamic range for all the
measuring applications. Table shows values of ADG[5:0] for three frequently used applications.
Table: FS511 ADC Typical Gain Setting
First Scale
Second Scale
Third Scale
ADG<5:0>
01_0011
11_0111
11_1000
Reference Voltage Gain(GREFi
1.0
1.25
1.25
Input Voltage Gain(GSIGi
1.0
1.25
0.1
The transfer function for each scale is as follows,
Equation 1
r
e f
x
R
E
F
i
SI
G
i
x
v
v
G
G
D
The gains for the reference voltages and input voltages shown in Table are approximate values. The
accurate gains for the reference voltages and input voltages can be found by careful calibration.



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