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FS9912 Datasheet(PDF) 22 Page - Fortune Semiconductor Corp. |
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FS9912 Datasheet(HTML) 22 Page - Fortune Semiconductor Corp. |
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22 / 34 page ![]() FS9912 Rev. 3.6 22/34 11.2 Power System Address Name Content 02CH NETD PUMPEN LBCEN BNDEN LCDEN REGEN GNDEN BIASEN 02DH SVD LB Voltage Doubler Voltage Regulator LCD Bias Bandgap Voltage Reference Analog Common Generator Bias Circuit CB CA VGG AGND VB Low Battery Compararor VDD VSS REGEN BIASEN Bias(to Analog Circuit) GNDEN PUMPEN Pump Clock LCDEN VC3,VC2,VC1 (To LCD Driver) BNDEN LBCEN LB 1uF 1uF 1uF 1uF 100k 1uF 10nF 100k BIASEN=1 will start the bias circuit of the analog circuit. When power on reset, BIASEN is 0 GNDEN=1 will start the internal analog common generator circuit, and the AGND voltage is about (vdd, vss)/2. PUMPEN=1 will start the voltage doubler circuit. VGG voltage is about 2VDD. PMPS (PT2MR [0]) will set the voltage doubler operation frequency: 0 is 2.7kHz, and 1 is 10kHz. REGEN=1 will start the internal voltage regulator. VDDA voltage is about 4V. LCDEN=1 will start the LCD driver bias circuit. The LCD bias voltages are RLCD, 2/3RLCD, 1/3RLCD, and vss respectively. BNDEN=1 will start the internal bandgap voltage reference. The output voltage (REFO, AGND) is about 1.2V. LBCEN=1 will start the low battery check comparator. The comparator inputs are VDD and REFO respectively, and the low battery check voltage is about 2.4V. 11.3 I/O Port 11.3.1 I/O Port1(PT1) Address Name Content 020H PT1 PT1 [7:0] 021H PT1EN PT1EN [7:0] 022H PT1PU PT1PU [7:0] 023H PT1MR E1M1 E1M0 E0M1 E0M0 |
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