DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Preliminary
7
Version: DM9801-DS-P02
March 20, 2000
Pin Description (Continued)
Pin No.
Pin Name
I/O
Description
Configuration and Control Interface:
64
RESET#
I
Reset:
Active Low input that initializes the DM9801. Should remain low for 10ms
after VCC has stabilized at 3.3Vdc (nominal) before it transitions high.
63
62
CONFIG0
CONFIG1
I
Configuration Select 1:0:
These input pins select the DM9801 configuration from a reset condition.
CONFIG1
CONFIG0
Configuration Selected
0
0
TXLED, RXLED and COLLED
configuration *
0
1
ACTLED, LNKLED and COLLED
configuration *
1
0
ACTLED, LNKLED and COLLED
configuration with MII Management
Register 0-6 emulation support *
1
1
ACTLED, LNKLED and COLLED
Configuration with MII Management
Register 0-6 emulation and 32 PHY
addresses support
*see the DM9801 description for a more detailed explanation
61
INTFSEL
I
Interface Select:
This pin selects either the MII interface or the GPSI interface.
0 = MII
1 = GPSI
60
CMDENA
I
Command Enable:
This pin enables a remote master node to alter the management register
values of the local DM9801.
59
SPDSEL
I
Speed Select:
This pin will select the 1M network speed.
0 = Low Speed
1 = High Speed
58
PWRSEL
I
Power Select:
This pin will select the 1M network power.
0 = Low Power
1 = High Power
65
TRIDRV
I
Tri-state all Outputs:
This pin, when asserted high, will tri-state all outputs (no effect on open-
drain outputs).
57
FWENA
I
Four Wire Interface Enable:
This pin, when asserted high, will enable the HNPB and HNNB driver pair
for operation. When low, the secondary drivers are powered down.
6
INT#
OD
Interrupt Request:
This pin will be asserted low when an interrupt condition exists in the
DM9801.
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